Semiconductor based logic devices often have a non-negligible power consumption due to leakage currents. Leakage currents occur notably in the interval between two subsequent state transitions. They typically persist even when the device is not performing any logical operations. Quite generally, leakage currents can only be reduced at the cost of operating speed. They are therefore a cause of concern, in particular with modern devices operating at high frequencies.
A well-known solution to saving energy is to set the device, or components thereof, in a so-called sleep state or reduced power mode, when there is a certain likelihood that the device or the components will be idle for a certain period. For example, it is known to switch off a volatile memory when it is expected that the memory will not be required in a near future. The data contained in the volatile memory may be transferred to a low-power memory, e.g. a permanent memory such as a hard disk, before the volatile memory is powered off. Thus the state of the volatile memory is conserved. When a return to normal operation is desired, the data is transferred back from the low-power memory to the volatile memory. A reduced power mode is sometimes referred to alternatively as an idle mode, stand-by mode, suspend mode, sleep mode, deep sleep mode, or hibernate mode.
State retention power gating (SRPG) is a technique that is widely employed in mobile integrated circuits (ICs). It allows a leakage reduction with fast recovery time. However, a problem with SRPG usually is an area overhead resulting from special flip-flops and additional power grids. The typical area penalty may about 10%. Furthermore, transferring large amounts of data from all flip-flops of a CPU typically requires a large dedicated memory and fast buses to this memory.
U.S. Pat. No. 7,164,301 by Ch. Chun proposes a particular technique for saving energy in a memory composed of flip-flops, each flip-flop comprising a latch for holding one bit of information. Each of the latches has a reset state, which is predefined by hardware as either logic TRUE (also termed HIGH or ONE or 1) or logic FALSE (also termed LOW or ZERO or 0). The memory is set into a reduced power mode by switching off those latches which are in their respective reset states. The memory is returned to normal mode by switching on the latches which were switched off and by resetting them into their respective reset states. Thus no information is lost. The method is implemented by providing each individual flip-flop with additional logical circuitry and a power switch (power gate).
U.S. patent application publication US 2008/0201592 describes a data processing apparatus comprising processing circuitry comprising a plurality of state retention cells in the form of scan chains. In response to a hibernate signal, a state of the processing circuitry is encrypted and saved to a non-volatile memory.
U.S. Pat. No. 7,626,434 discloses a low leakage state retention circuit.
U.S. Pat. No. 6,336,161 describes a computer configuration system with state restoration from non-volatile semiconductor memory.